A wide variety of solid-state imagers use CCD output shift registers to convert to serial-in-time formal charge packets loaded parallel-in-time into respective ones of its successive charge transfer stages. These CCD output shift registers are parallel-input/serial-output CCD registers. Generally, the charge packets supplied serially in time from the CCD output shift register are then sensed in a charge sensing stage to generate samples of a video output signal voltage (or current). Line arrays of photosensors can transfer their respective photoresponses through a parallel-transfer register to side-load the charge transfer stages of the CCD output shift register, for example. Certain metal-oxide-semiconductor (MOS) imagers have their MOS sensors polled a line at a time to side-load the CCD output shift register. CCD imagers of interline transfer, of field transfer, and of line transfer types typically use side-loaded CCD output shift registers.
The charge sensing circuitry in such solid-state imagers detects minute variations in the size of successive charge packets serially supplied from the CCD output shift register. This is done in the presence of substantially large unwanted signals. A principal source of these signals is associated with the CCD shift register portions of the solid-state imager being disposed in a semiconductive substrate, which substrate is very difficult to hold at a fixed potential because of the presence of clocking signals of several volts being capacitatively coupled to it. Extensive selective filtering is customarily required to separate the wanted output signal from the unwanted clocking signal, or "clock noise" as it is commonly termed.
This selective filtering may be provided by low-pass filtering to discriminate against clocking signal. Alternatively, this selective filtering may be provided by synchronous detection at a harmonic of CCD output shift register clocking rate, followed by low-pass filtering. The low-pass filtering processes may be linear processes or may involve non-linear processes, such as sampling and holding.
Arrangements for cancellation of clock noise are known in the art, also. Caywood in U.S. Pat. No. 3,806,729, issued APR. 23, 1974, and entitled "CHARGE COUPLED DEVICE IR IMAGER" describes the collection of charge elements alternately from the scene and from a uniform background reference source in the columnar shift registers that are components of the image register of a field transfer CCD imager. The imager is provided with two CCD output shift registers parallelly disposed at the ends of the columnar shift registers that are components of its field storage register. A row of charge elements descriptive of the image is transferred in parallel from the columnar shift registers to respective ones of the charge transfer stages in one of the CCD output shift registers, and an adjacent row of charge elements descriptive of background reference source (provided by masked rows in the image register) is transferred in parallel from the columnar shift registers to respective ones of the charge transfer stages in the other of the CCD output shift registers. The first of these parallel transfers is through the charge transfer stages of the CCD output shift register proximate to the field storage register, to the charge transfer stages of the CCD output shift register distal from the field storage register. After both being side-loaded, the two output shift registers are forward clocked in synchronism. Each pair of charge elements concurrently clocked from the output shift registers are differentially sensed. This differential sensing not only reduces background variations (chiefly accumulated dark current), but also reduces clock noise.
A problem with the Caywood arrangement is that it doubles the number of rows (and, consequently, the number of charge transfer stages) in the imager. The attendant doubling of the imager die size makes the Caywood approach infeasible. The problem of dark current noise cancellation has subsequently been solved in ways that do not require great increase in die size. Better ways of effecting dark current cancellation are described by P.S. Levine in U.S. Pat. No. 4,496,982, issued Jan. 29, 1985, and entitled "COMPENSATION AGAINST FIELD SHADING IN VIDEO FROM FIELD-TRANSFER CCD IMAGERS", by D.D. Crawshaw in U.S. Pat. No. 4,498,105, issued Feb. 5, 1985, and entitled "FIELD-TRANSFER CCD IMAGERS WITH REFERENCE-BLACK-LEVEL GENERATION CAPABILITY"; and by P.A. Levine in U.S. patent application Ser. No. 687,368, filed Dec. 28, 1984, entitled "CHARGE-STORAGE-WELL DARK CURRENT ACCUMULATOR WITH CCD CIRCUITRY", and assigned to RCA Corporation. U.S. Pat. Nos. 4,496,982 and 4,498,105 are incorporated herein by reference.
The present invention concerns a way of suppressing clock noise in the output video signal from a solid-state imager without greatly increasing the size of the imager. The present invention is also concerned with the problem of suppressing fat zero bias charge which may have been added to charge packets descriptive of image elements upon their admission to the output shift register. Such addition of bias charge is done in order to improve transfer efficiency through the output shift register for low-level charge packets.